

module TB (SW,LEDR,LEDG, KEY,HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7);

input SW[17:0];
output LEDR[17:0];
output LEDG[8:0];
input KEY[4:0];
output HEX0[6:0];
output HEX1[6:0];
output HEX2[6:0];
output HEX3[6:0];
output HEX4[6:0];
output HEX5[6:0];
output HEX6[6:0];
output HEX7[6:0];

wire [17:0] SW;
wire [17:0] LEDR;
wire [8:0] LEDG;

wire KEY[4:0];
wire HEX0[6:0];
wire HEX1[6:0];
wire HEX2[6:0];
wire HEX3[6:0];
wire HEX4[6:0];
wire HEX5[6:0];
wire HEX6[6:0];
wire HEX7[6:0];


assign LEDR = SW;

integer i;
integer b;

reg [31:0] rA;
reg [31:0] rB;
reg [4:0] rC;
reg [2:0] FLAGS;
reg [31:0] result;
CHIP chip(.A(rA), .B(rB), .OP(rC), .OUT(result), .FLAG(FLAGS));

	initial begin	
		clear(); //Reseta displays
		b = 0;
	end
	
	always @ (negedge KEY[3] or negedge KEY[2] or negedge KEY[1] or negedge KEY[0]) begin	
		if (KEY[3] == 0) begin
			put (-1, HEX7);
			put (-1, HEX6);
			put (-1, HEX5);
			rA = SW[15:0];
			b = rA;
			put (1, HEX4);
		end else if (KEY[2] == 0) begin
			put (-1, HEX7);
			put (-1, HEX6);
			put (-1, HEX5);
			rB = SW[15:0];
			b = rB;
			put (2, HEX4);
		end else if (KEY[1] == 0) begin
			put (-1, HEX7);
			put (-1, HEX6);
			put (-1, HEX5);
			rC = SW[3:0];
			b = rC;
			put (3, HEX4);
		end else begin	
			b = result;
			put (b >> 28, HEX7);
			put ((b >> 24) & 4'hFF, HEX6);
			put ((b >> 20) & 4'hFF, HEX5);
			put ((b >> 16) & 4'hFF, HEX4);
			LEDG[2] = FLAGS[2];
			LEDG[1] = FLAGS[1];
			LEDG[0] = FLAGS[0];
		end
		put ((b >> 12) & 4'hFF, HEX3);
		put ((b >> 8) & 4'hFF, HEX2);
		put ((b >> 4) & 4'hFF, HEX1);
		put (b & 4'hFF, HEX0);		
	end

task clear;
	begin 
		put (-1, HEX0);
		put (-1, HEX1);
		put (-1, HEX2);
		put (-1, HEX3);
		put (-1, HEX4);
		put (-1, HEX5);
		put (-1, HEX6);
		put (-1, HEX7);
	end
endtask

task put;
	input a;
	output b[6:0];
	integer a;
	begin 
		case (a)
			0: begin
				b[0] = 1'b0;
				b[1] = 1'b0;
				b[2] = 1'b0;
				b[3] = 1'b0;
				b[4] = 1'b0;
				b[5] = 1'b0;
				b[6] = 1'b1;
			end
			1: begin 
				b[0] = 1'b1;
				b[1] = 1'b0;
				b[2] = 1'b0;
				b[3] = 1'b1;
				b[4] = 1'b1;
				b[5] = 1'b1;
				b[6] = 1'b1;
			end
			2: begin
				b[0] = 1'b0;
				b[1] = 1'b0;
				b[2] = 1'b1;
				b[3] = 1'b0;
				b[4] = 1'b0;
				b[5] = 1'b1;
				b[6] = 1'b0;
			end
			3: begin
				b[0] = 1'b0;
				b[1] = 1'b0;
				b[2] = 1'b0;
				b[3] = 1'b0;
				b[4] = 1'b1;
				b[5] = 1'b1;
				b[6] = 1'b0;
			end
			4: begin
				b[0] = 1'b1;
				b[1] = 1'b0;
				b[2] = 1'b0;
				b[3] = 1'b1;
				b[4] = 1'b1;
				b[5] = 1'b0;
				b[6] = 1'b0;
			end
			5: begin
				b[0] = 1'b0;
				b[1] = 1'b1;
				b[2] = 1'b0;
				b[3] = 1'b0;
				b[4] = 1'b1;
				b[5] = 1'b0;
				b[6] = 1'b0;
			end
			6: begin
				b[0] = 1'b0;
				b[1] = 1'b1;
				b[2] = 1'b0;
				b[3] = 1'b0;
				b[4] = 1'b0;
				b[5] = 1'b0;
				b[6] = 1'b0;
			end
			7: begin
				b[0] = 1'b0;
				b[1] = 1'b0;
				b[2] = 1'b0;
				b[3] = 1'b1;
				b[4] = 1'b1;
				b[5] = 1'b1;
				b[6] = 1'b1;
			end
			8: begin
				b[0] = 1'b0;
				b[1] = 1'b0;
				b[2] = 1'b0;
				b[3] = 1'b0;
				b[4] = 1'b0;
				b[5] = 1'b0;
				b[6] = 1'b0;
			end
			9: begin
				b[0] = 1'b0;
				b[1] = 1'b0;
				b[2] = 1'b0;
				b[3] = 1'b0;
				b[4] = 1'b1;
				b[5] = 1'b0;
				b[6] = 1'b0;
			end
			10: begin
				b[0] = 1'b0;
				b[1] = 1'b0;
				b[2] = 1'b0;
				b[3] = 1'b1;
				b[4] = 1'b0;
				b[5] = 1'b0;
				b[6] = 1'b0;
			end
			11: begin
				b[0] = 1'b1;
				b[1] = 1'b1;
				b[2] = 1'b0;
				b[3] = 1'b0;
				b[4] = 1'b0;
				b[5] = 1'b0;
				b[6] = 1'b0;
			end
			12: begin
				b[0] = 1'b0;
				b[1] = 1'b1;
				b[2] = 1'b1;
				b[3] = 1'b0;
				b[4] = 1'b0;
				b[5] = 1'b0;
				b[6] = 1'b1;
			end
			13: begin
				b[0] = 1'b1;
				b[1] = 1'b0;
				b[2] = 1'b0;
				b[3] = 1'b0;
				b[4] = 1'b0;
				b[5] = 1'b1;
				b[6] = 1'b0;
			end
			14: begin
				b[0] = 1'b0;
				b[1] = 1'b1;
				b[2] = 1'b1;
				b[3] = 1'b0;
				b[4] = 1'b0;
				b[5] = 1'b0;
				b[6] = 1'b0;
			end
			15: begin
				b[0] = 1'b0;
				b[1] = 1'b1;
				b[2] = 1'b1;
				b[3] = 1'b1;
				b[4] = 1'b0;
				b[5] = 1'b0;
				b[6] = 1'b0;
			end
			default: begin
				b[0] = 1'b1;
				b[1] = 1'b1;
				b[2] = 1'b1;
				b[3] = 1'b1;
				b[4] = 1'b1;
				b[5] = 1'b1;
				b[6] = 1'b1;
			end
		endcase
	end
endtask

endmodule

